
ASML Secures TSMC and Samsung for High-NA EUV Machines: What the AI Boom Means for Chip Equipment Makers
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Key Takeaways
- ASML Holding receives binding commitments from Samsung Electronics and TSMC on September 8, 2026 for the adoption of High-NA EUV lithography machines, each costing around 400 million US dollars.
- Samsung plans to deploy High-NA technology from 2028 for DRAM production, while TSMC begins rollout from 2030 for advanced logic chips, and Intel has been using the machines since July 2026.
- High-NA EUV systems increase the numerical aperture of the optical path and enable significantly finer exposure patterns than standard EUV, allowing more complex AI chips to be manufactured on smaller structures.
- ASML, Samsung, TSMC, and Intel agree to switch from 6-inch to 12-inch photomasks, which according to ASML CTO Marco Pieters could increase the throughput of High-NA machines by 40 percent.
- TSMC CEO C.C. Wei emphasizes industry cooperation to overcome technical barriers before they become economic obstacles for the semiconductor industry.
- ASML is the only manufacturer worldwide of EUV lithography equipment, which is necessary for the manufacture of the most advanced AI accelerators and comparable chips.
ASML Holding NV receives significant commitments from Samsung Electronics and Taiwan Semiconductor Manufacturing Company (TSMC) on September 8, 2026 for the adoption of High-NA EUV lithography machines. Both chipmakers thus join Intel, which has been using the technology since July 2026. The announcements mark a coordinated industry step to address growing demand for AI chips.
Rollout Timeline: Samsung Starts 2028, TSMC Follows 2030
Samsung plans to deploy High-NA technology starting in 2028 for DRAM production. The South Korean conglomerate, as the world's leading memory manufacturer, aims to expand its DRAM scaling roadmap and improve process efficiency with this step. TSMC, which manufactures chips for customers like Nvidia, Apple, Advanced Micro Devices, and Qualcomm, will begin using the machines from 2030 onwards for advanced logic chips.
Each High-NA EUV machine costs approximately 400 million US dollars. The industry cites investment volumes in the double-digit billions per installation wave for capacity building. The decisions by the three largest chipmakers worldwide demonstrate that the next generation of manufacturing technology is transitioning from theoretical discussion into concrete investment cycles.
What High-NA EUV Differs From Previous Technology
High NA stands for "High Numerical Aperture" and increases the numerical aperture of the optical path. This allows the machines to expose significantly finer and more detailed patterns on silicon wafers than standard EUV systems. The improved resolution for complex pattern geometries enables the manufacture of more complex chips for AI applications on smaller structures.
ASML introduced Low-NA EUV technology in 2019. TSMC had been hesitant to adopt the more expensive High-NA machines, arguing that cost efficiency did not yet justify the productivity gains. Today's commitments signal a paradigm shift in this calculation.
Photomask Switch Targets 40 Percent Throughput Increase
In parallel with High-NA adoption, ASML, Samsung, TSMC, and Intel agree on a technological format change for photomasks. These key components function like woodcut blocks for repeatedly printing patterns onto silicon wafers. The current standard of 6-inch photomasks is to be gradually transitioned to 12-inch versions.
TSMC plans to establish a test line for the new format by 2031 and production deployment with High-NA tools from 2033. Marco Pieters, Chief Technology Officer at ASML, explained that the new mask technology could increase the throughput of High-NA machines by 40 percent while simplifying the design process. TSMC will initially start in 2030 with standard 6-inch masks before the transition is made.
AI Demand as Fundamental Driver
AI applications are fundamentally driving semiconductor demand. In AI servers, DRAM and logic often jointly determine bottleneck costs. Faster and cheaper memory scaling can reduce system pressure from rising compute and data rates. Samsung's use of High-NA in DRAM production targets exactly this bottleneck.
AI workloads demand more computational power in increasingly smaller structures. This shifts bottlenecks to exposure systems, where the layout is first transferred to the wafer. Demand concentrates on AI accelerators such as Nvidia's H200 and planned Blackwell processors, which are ordered by hyperscalers.
ASML Monopoly and Strategic Market Position
ASML is the only company worldwide that manufactures EUV lithography equipment. These machines are necessary for manufacturing the world's most advanced AI accelerators and similar chips. The monopoly position gives the Dutch company a unique position in the semiconductor supply chain.
TSMC CEO C.C. Wei stated: "TSMC has always believed in the power of collaboration to overcome technical barriers before they become economic barriers for the semiconductor industry." The statement illustrates that the industry acts in a coordinated manner to address technical hurdles collectively before they become economic obstacles.
Implications for Chipmakers and Suppliers
Customer decisions increase pressure on production capacity planning across the entire supply chain. Chipmakers must invest heavily in cutting-edge capacity to supply AI chip designers like Nvidia. The billion-dollar commitments reflect a fundamental shift in foundry economics.
The initial customer commitments set off capacity and technology cycles that will shape the semiconductor industry for years to come. The coordinated approach by Samsung, TSMC, and Intel shows that the industry regards High-NA EUV technology as indispensable for meeting AI-driven demand.