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ASML Wins TSMC and Samsung for New EUV Machines: What the Deal Means for Chip Investors
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ASML Wins TSMC and Samsung for New EUV Machines: What the Deal Means for Chip Investors

By Redaktion aktie.com

This article was created with the help of artificial intelligence.

Key Takeaways

  • On September 8, 2026, TSMC and Samsung committed to integrating ASML's High-NA EUV lithography machines into their production roadmaps starting in 2028 and 2030 respectively, to meet rising AI demand.
  • A single High-NA EUV machine costs up to 400 million US dollars, while installation waves can require double-digit billion-dollar amounts according to industry sources.
  • Samsung plans to deploy High-NA technology starting in 2028 for DRAM production and from 2030 onwards for gradual integration into its DRAM scaling roadmap, while TSMC focuses on advanced logic chips for AI applications beginning in 2030.
  • High-NA EUV systems enable finer focusing and smaller, more complex layer patterns on wafers than previous standard EUV setups through increased numerical aperture, utilizing significantly larger 12-inch photomasks.
  • The customer decisions by Samsung and TSMC are viewed by the industry as a clear signal to the entire semiconductor equipment manufacturing sector and translate theoretical discussions into concrete capacity and technology cycles.

TSMC and Samsung announced commitments on September 8, 2026 to incorporate ASML's High-NA EUV lithography machines into their production roadmaps. Samsung plans deployment starting in 2028, with gradual adoption from 2030 onwards, while TSMC plans deployment starting in 2030. The announcements come against the backdrop of rising AI demand and mark a technological turning point for the semiconductor industry.

How High-NA EUV Technology Differs from Standard Systems

High-NA EUV (High Numerical Aperture Extreme Ultraviolet) is an advancement of EUV lithography that enables smaller and more complex structures on semiconductor wafers through an increased numerical aperture of the optical path. Unlike standard EUV systems, the technology allows finer focusing and better resolution for challenging pattern geometries. This results in denser transistor arrangements, particularly required for AI chips and the scaling of DRAM memory.

A key technical difference lies in the shift to significantly larger 12-inch photomasks. Highly detailed patterns are imaged onto wafers by High-NA systems and subsequently used in multiple process steps to form the actual structures in the chip. The technology relies not primarily on the light source itself, but on the entire optical system and imaging principle as the decisive factor.

Specific Timelines and Applications for Both Manufacturers

Samsung is focusing on DRAM production and plans to use High-NA technology starting in 2028 for production and from 2030 onwards for gradual integration into the DRAM scaling roadmap. This is market-relevant because DRAM and logic jointly determine the bottleneck costs in AI servers. Faster and more cost-effective memory scaling can reduce system pressure from rising computing and data rates.

TSMC complements this strategy with a focus on advanced logic chips for AI applications starting in 2030. Intel is already using the High-NA EUV machines and serves as a bellwether for other manufacturers. The staggered timing reflects different production requirements and investment cycles.

Investment Volume and Economic Dimensions

A single High-NA EUV machine costs up to 400 million US dollars. These high individual costs explain why manufacturers and suppliers carefully assess when and how many tools they can install. According to industry sources, installation wave investments in the double-digit billion-dollar range per wave are possible.

The commitments from Samsung and TSMC increase planning certainty for all parties involved, while ASML's specific rollout plan remains partly open. The industry describes increased planning pressure on capacities given the large investment sums and long lead times for machine production.

AI Demand as Central Driver

The global boom in AI applications and surging demand for powerful AI hardware are the main drivers of this technology shift. The commitments from Samsung and TSMC signal that computing performance requirements for AI workloads demand smaller structures in increasingly complex designs.

Bottlenecks are shifting to exposure systems that can "print" these layouts in the first place. ASML's High-NA systems serve as a central technological lever for the next semiconductor manufacturing generation. The announcements translate theoretical discussions about the next technology generation into concrete capacity and technology cycles.

Signal Effect for the Semiconductor Industry and ASML Investors

The customer decisions by Samsung and TSMC are viewed as a clear signal to the entire semiconductor equipment manufacturing sector. The commitments reflect the ongoing trust of customers in the innovation capability of the Dutch equipment manufacturer.

For investors in ASML stock, the commitments represent a stabilization of the revenue outlook in a high-priced product segment. The staggered timing of deployments (2028 for Samsung DRAM, 2030 for TSMC logic) enables medium-term predictability of order intake. The high unit prices and double-digit billion-dollar investment volume per installation wave underscore the strategic importance of the High-NA platform for ASML's business development.

Historical Context: Continuity of Customer Relationships

ASML began developing EUV lithography in the 2010s. In 2012, Intel, TSMC, and Samsung participated in financing systems for increasingly smaller structures – a continuity that continues in the current High-NA commitments from September 8, 2026. This long-term collaboration between ASML and the three leading chip manufacturers worldwide forms the foundation for the shared technology roadmap.

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